The present invention relates to semiconductor design technologies, and in particular, to a data output circuit of a semiconductor device. More particularly, the present invention relates to a data output circuit of a semiconductor device, which is capable of stably outputting data while suppressing a simultaneous switching output (SSO) noise.
FIG. 1 is a circuit diagram of a conventional data output circuit of a semiconductor device.
Referring to FIG. 1, a conventional data output circuit of a semiconductor device includes a plurality of pre-drive units 100A, 100B, 100C and 100D, a plurality of pull-up main driving units 120A, 120B, 120C and 120D, and a plurality of pull-down main driving units 140A, 140B, 140C and 140D. The pre-drive units 100A, 100B, 100C and 100D generate a plurality of drive control signals DRV_CTL0, DRV_CTL1, DRV_CTL2 and DRV_CTL3 in response to a plurality of bits DATA<0>, DATA<1>, DATA<2> and DATA<3> of a data code DATA<0:3>, respectively. The pull-up main driving units 120A, 120B, 120C and 120D control the connections between a power supply voltage terminal VDDQ and a plurality of data output pads DQ0, DQ1, DQ2 and DQ3 in response to the drive control signals DRV_CTL0, DRV_CTL1, DRV_CTL2 and DRV_CTL3, respectively. Herein, the data output pads DQ0, DQ1, DQ2 and DQ3 are terminated to the power supply voltage terminal VDDQ through a plurality of data output pins DQ0P, DQ1P, DQ2P and DQ3P, respectively. The pull-down main driving units 140A, 140B, 140C and 140D pull-down drive the data output pads DQ1, DQ1, DQ2 and DQ3 by pull-down sink currents PDI_SINK_0, PDI_SINK_1, PDI_SINK_2 and PDI_SINK_3 of predetermined intensities sinking through a ground voltage terminal VSSQ in response to the drive control signals DRV_CTL0, DRV_CTL1, DRV_CTL2 and DRV_CTL3, respectively. Herein, the data output pads DQ0, DQ1, DQ2 and DQ3 are terminated to the power supply voltage terminal VDDQ through the data output pins DQ0P, DQ1P, DQ2P and DQ3P, respectively.
Based on the above configuration, an operation of the conventional data output circuit is described hereinafter.
As illustrated in FIG. 1, because the data output pads DQ0, DQ1, DQ2, and DQ3 are terminated to the power supply voltage terminal VDDQ through a power supply voltage input pin VDDQP, the conventional data output circuit maintains a power supply voltage (VDD) level while data are not outputted.
When the inputted data code DATA<0>/DATA<1>/DATA<2>/DATA<3> has a value of ‘0’, the pre-drive unit 100A/100B/100C/100D outputs the drive control signal DRV_CTL0/DRV_CTL1/DRV_CTL2/DRV_CTL3 with the power supply voltage (VDD) level.
When the drive control signal DRV_CTL0/DRV_CTL1/DRV_CTL2/DRV_CTL3 has the power supply voltage (VDD) level, the pull-up main driving unit 120A/120B/120C/120D forms an open circuit between the power supply voltage terminal VDDQ and the data output pad DQ0/DQ1/DQ2/DQ3, so that the power supply voltage terminal VDDQ and the data output pad DQ0/DQ1/DQ2/DQ3 have different voltage levels. Also, the pull-down main driving unit 140A/140B/140C/140D forms a short circuit between the ground voltage terminal VSSQ and the data output pad DQ0/DQ1/DQ2/DQ3, so that the pull-down sink current PDI_SINK_0/PDI_SINK_1/PDI_SINK_2/PDI_SINK_3 flows to the ground voltage terminal VSSQ from the data output pad DQ0/DQ1/DQ2/DQ3.
That is, when the data code DATA<0>/DATA<1>/DATA<2>/DATA<3> has a value of ‘0’ and thus the drive control signal DRV_CTL0/DRV_CTL1/DRV_CTL2/DRV_CTL3 has the power supply voltage (VDD) level, the power supply voltage terminal VDDQ is disconnected from the data output pad DQ0/DQ1/DQ2/DQ3 and the pull-down sink current PDI_SINK 0/PDI_SINK 1/PDI_SINK_2/PDI_SINK_3 flows to the ground voltage terminal VSSQ from the data output pad DQ0/DQ1/DQ2/DQ3. Therefore, the voltage level of the data output pad DQ0/DQ1/DQ2/DQ3 becomes lower than that of the power supply voltage terminal VDDQ, thus causing a logic low level.
For reference, because the power supply voltage terminal VDDQ is disconnected from the data output pad DQ0/DQ1/DQ2/DQ3, even when the data output pad DQ0/DQ1/DQ2/DQ3 is terminated to the power supply voltage terminal VDDQ, the pull-down sink current PDI_SINK_0/PDI_SINK_1/PDI_SINK_2/PDI_SINK_3 flows from the data output pad DQ0/DQ1/DQ2/DQ3 to the ground voltage terminal VSSQ and thus the voltage level of the data output pad DQ0/DQ1/DQ2/DQ3 becomes lower than that of the power supply voltage terminal VDDQ.
When the inputted data code DATA<0>/DATA<1>/DATA<2>/DATA<3> has a value of ‘1’, the pre-drive unit 100A/100B/100C/100D outputs the drive control signal DRV_CTL0/DRV_CTL1/DRV_CTL2/DRV_CTL3 with the ground voltage (VSS) level.
When the drive control signal DRV_CTL0/DRV_CTL1/DRV_CTL2/DRV_CTL3 has the ground voltage (VSS) level, the pull-up main driving unit 120A/120B/120C/120D forms a short circuit between the power supply voltage terminal VDDQ and the data output pad DQ0/DQ1/DQ2/DQ3, so that the power supply voltage terminal VDDQ and the data output pad DQ0/DQ1/DQ2/DQ3 have the same power supply voltage (VDD) level. Also, the pull-down main driving unit 140A/140B/140C/140D forms an open circuit between the ground voltage terminal VSSQ and the data output pad DQ0/DQ1/DQ2/DQ3, so that the pull-down sink current PDI_SINK_0/PDI_SINK_1/PDI_SINK_2/PDI_SINK_3 does not flow to the ground voltage terminal VSSQ from the data output pad DQ0/DQ1/DQ2/DQ3.
That is, when the data code DATA<0>/DATA<1>/DATA<2>/DATA<3> has a value of ‘1’ and thus the drive control signal DRV_CTL0/DRV_CTL1/DRV_CTL2/DRV_CTL3 has the ground voltage (VSS) level, the data output pad DQ0/DQ1/DQ2/DQ3 and the power supply voltage terminal VDDQ having the same power supply voltage (VDD) level are connected to each other and the ground voltage terminal VSSQ is disconnected from the data output pad DQ0/DQ1/DQ2/DQ3, so that the pull-down sink current PDI_SINK_0/PDI_SINK_1/PDI_SINK_2/PDI_SINK_3 does not flow to the ground voltage terminal VSSQ from the data output pad DQ0/DQ1/DQ2/DQ3. Therefore, the voltage level of the data output pad DQ0/DQ1/DQ2/DQ3 becomes equal to that of the power supply voltage terminal VDDQ, thus causing a logic high level.
For reference, no current flows from the power supply voltage terminal VDDQ to the data output pad DQ0/DQ1/DQ2/DQ3, because the ground voltage terminal VSSQ is disconnected from the data output pad DQ0/DQ1/DQ2/DQ3 and simultaneously the data output pad DQ0/DQ1/DQ2/DQ3 automatically becomes the power supply voltage (VDD) level through the termination-connected power supply voltage terminal VDDQ, that is, because no current flows from the power supply voltage terminal VDDQ with the same power supply voltage VDD to the data output pad DQ0/DQ1/DQ2/DQ3.
As described above, the conventional data output circuit drives the data output pad DQ0/DQ1/DQ2/DQ3 at the power supply voltage (VDD) level or at the ground voltage (VSS) level according to the value of the data code DATA<0>/DATA<1>/DATA<2>/DATA<3>. As illustrated in FIG. 1, because the data output pad DQ0/DQ1/DQ2/DQ3 is terminated to the power supply voltage (VDD) level (which is generally called a pseudo open drain termination state), the conventional data output circuit does not include an operation of directly driving the data output pad DQ0/DQ1/DQ2/DQ3 at the power supply voltage (VDD) level, which may vary depending on the voltage level terminating the data output pad DQ0/DQ1/DQ2/DQ3.
For example, when the data output pad DQ0/DQ1/DQ2/DQ3 is terminated to the ground voltage (VSS) level (which is generally called a pseudo open source termination state), the conventional data output circuit includes an operation of driving the data output pad DQ0/DQ1/DQ2/DQ3 at the power supply voltage (VDD) level but does not include an operation of driving the data output pad DQ0/DQ1/DQ2/DQ3 at the ground voltage (VSS) level. When the data output pad DQ0/DQ1/DQ2/DQ3 is terminated to the intermediate voltage level between the power supply voltage (VDD) level and the ground voltage (VSS) level (which is generally called a center tap termination state), the conventional data output circuit includes an operation of driving the data output pad DQ0/DQ1/DQ2/DQ3 at the power supply voltage (VDD) level and an operation of driving the data output pad DQ0/DQ1/DQ2/DQ3 at the ground voltage (VSS) level.
Meanwhile, a simultaneous switching output (SSO) noise may occur in a data output circuit of a semiconductor device because a plurality of pads and a plurality of pins in the data output circuit simultaneously switch from a power supply voltage (VDD) level to a ground voltage (VSS) level, or from the ground voltage (VSS) level to the power supply voltage (VDD) level.
That is, when a plurality of data are outputted through the pads and the pins, if most of the data may have the power supply voltage (VDD) level at a first time point and have the ground voltage (VSS) level at a second time point subsequent to the first time point, a large amount of source current may suddenly flow into a ground voltage terminal VSSQ, so that some of the data may fail to switch from the power supply voltage (VDD) level to the ground voltage (VSS) level or switch later than a predetermined time point. This phenomenon is called a simultaneous switching output (SSO) noise.
Also, even when most of the data switch to the ground voltage (VSS) level at the second time point, if most of the data may have the power supply voltage (VDD) level at a third time point subsequent to the second time point, a large amount of sink current suddenly flows into a power supply voltage terminal VDDQ, so that some of the data may fail to switch from the ground voltage (VSS) level to the power supply voltage (VDD) level or switch later than a predetermined time point. This phenomenon is also called a simultaneous switching output (SSO) noise.
Such a simultaneous switching output (SSO) noise acts as a very important factor in the processing speed and the designing of a semiconductor device. Examples of the phenomenon caused by the simultaneous switching output (SSO) noise may include ground bounce and clock waveform degradation.
That is, the simultaneous switching output (SSO) noise may distort the data outputted from the data output circuit, thus failing to output normal data.
Like a data bus inversion scheme or an 8/10b coding scheme, a conventional scheme uses a noise preventing pad or pin as well as a plurality of pads or a plurality of pins for outputting a plurality of data, thereby preventing a simultaneous switching output (SSO) noise from occurring in the data outputted through the plurality of pads or the plurality of pins.
The data bus inversion scheme or the 8/10b coding scheme is well known in the art and thus its detailed description is not provided herein.
The data bus inversion scheme or the 8/10b coding scheme has a limitation in that it may additionally use a noise preventing pad or pin. This limitation becomes more severe as the number of data output pads or pins increases with an increase in the scale and complexity of a semiconductor device. This causes an excessive increase in the number of noise preventing pads or pins that must be provided in addition to data output pads or pins.
Such an excessive increase in the number of pads or pins in a semiconductor device may require a significantly increased area of the semiconductor device, which may cause a significantly increased fabrication cost of the semiconductor device.